pub fn moe_expert_gemv_silu_down_2x(
gpu: &dyn GpuBackend,
kernel: KernelHandle,
gate_out: DevicePtr,
up_out: DevicePtr,
packed_ptrs: DevicePtr,
scale_ptrs: DevicePtr,
scale2_vals: DevicePtr,
output: DevicePtr,
expert_indices: DevicePtr,
n: u32,
k: u32,
top_k: u32,
stream: u64,
) -> Result<()>Expand description
Register-tiled fused SiLU+down expert GEMV: 2 output rows per thread.
Same as silu_down but each thread computes 2 adjacent output rows, reusing the SiLU(gate)*up activation from registers. Doubles weight reads per iteration for better LPDDR5X bandwidth utilization.
Grid: (ceil(N/8), top_k, 1) Block: (128, 1, 1)