pub struct DflashProposerState {Show 15 fields
pub block_table: Vec<u32>,
pub seq_len: usize,
pub last_num_drafted: usize,
pub prefill_done: bool,
pub ctx_hidden_acc: DevicePtr,
pub ctx_len: usize,
pub last_num_accepted: usize,
pub skip_next_decode_append: bool,
pub max_ctx_len: usize,
pub ctx_slot_bytes: usize,
pub block_table_dev: Option<DevicePtr>,
pub ctx_count_drafter: usize,
pub max_ctx_count_drafter: usize,
pub ctx_committed: usize,
pub ctx_positions: Vec<i32>,
}Expand description
Per-sequence DFlash drafter state. One paged KV cache per drafter layer
(8 typical), shared block table across layers since attention shape is
identical layer-to-layer for a vanilla Qwen3 architecture. Mirrors
MtpProposerState in spirit; the multi-layer cache keeps it distinct.
Fields§
§block_table: Vec<u32>Block table for the drafter’s KV cache (shared across all drafter layers).
seq_len: usizeCurrent logical sequence length in the drafter’s KV cache. Tracks how
many target-aligned positions have been written via
precompute_and_store_context_kv.
last_num_drafted: usizeDrafts produced in the last propose() call. after_verify consults
this to know how many KV positions to roll back when the accept
prefix is shorter than γ.
prefill_done: boolWhether the prompt-time precompute_and_store_context_kv has been
called. The first propose() after model build needs to run prefill
over the full prompt’s captured hiddens; subsequent steps incrementally
append the latest accepted tokens’ projections.
Multi-token accumulator for captured target hidden states. Layout:
[max_ctx_len, 5 * target_hidden] BF16 packed. The scheduler appends
the model’s dflash_hidden_save (latest decoded position’s 5 hiddens)
into slot ctx_len after each successful verify. propose() reads
the full populated prefix and projects all positions through fc
at forward time. Sized for max_seq_len total positions; not
circular — fail-fast if exceeded (drafter can’t handle longer
context than allocated).
ctx_len: usizeNumber of populated slots in ctx_hidden_acc. Capped at max_ctx_len.
last_num_accepted: usizeDrafts accepted in the verify that immediately preceded this propose.
Set by after_verify so propose can label row-0 with its TRUE position.
skip_next_decode_append: boolEAGLE-fix one-shot: when set, the next propose() skips its internal
decode-append because the verify step (K=2 accept) already appended
row 0 + row 1 in EAGLE order before calling propose. Consumed (reset to
false) by propose. Set on the EAGLE-fix path, which is DEFAULT-ON
(ATLAS_DFLASH_EAGLE_FIX=0 is the kill switch, not =1 the opt-in ,
see verify_k2_step.rs and verify_dflash_step.rs, both != Some("0")).
max_ctx_len: usizeAllocation cap for ctx_hidden_acc (in slot count). Mirrors the
max_seq_len build arg so we can clamp without re-fetching it.
ctx_slot_bytes: usizeWidth (bytes) of one ctx_hidden_acc slot — 5 * target_hidden * bf16.
Stored to avoid re-deriving on every append.
block_table_dev: Option<DevicePtr>Device-side block table for the drafter’s paged KV cache. Allocated
once at first propose with enough u32 slots to cover max_seq_len
at block_size=16. Read by prefill_attention_paged_dflash to map
logical block indices to physical pool block indices. Mirrors the
host-side block_table Vec, copied to GPU after each alloc_block.
ctx_count_drafter: usizeNumber of paged-cache slots populated with ctx K/V for this sequence.
Distinct from ctx_len (which counts target_hidden_acc slots). The
drafter writes one ctx K/V slot per accepted target token; the
γ-block then attends over [0..ctx_count_drafter+γ). Bumped by γ
per propose (γ slots written for the noise rows) and trimmed in
after_verify by (γ - num_accepted).
max_ctx_count_drafter: usizeCap for ctx_count_drafter. Mirrors block_table.len() * block_size.
ctx_committed: usizePhase I — incremental ctx precompute watermark. Number of ctx slots
[0..ctx_committed) whose K/V is already valid in the paged cache
from a prior propose. Each step we only precompute the new tail
[ctx_committed..ctx_len) instead of rebuilding the whole prefix
(the old O(ctx_len²) waste — see design doc §18). Reset to the
current ctx_len on any rewind so stale slots can’t be read.
0 forces a full rebuild (first propose, or the debug escape hatch).
ctx_positions: Vec<i32>Phase I (v2) — per-slot TRUE absolute decoded position, stamped once
when a ctx slot is appended and never recomputed. Indexed by ctx
slot (parallel to ctx_hidden_acc slots, len == ctx_len). This is
the vLLM convention: a cached token’s rope position is fixed at
insert time, so committed slots never go stale when later accepts
shift the live position. Replaces the sliding `absolute_start_pos
- i
formula inprecompute_ctx_kv. Prefill positions are seeded0..prompt_leninupdate_dflash_ctx_len_after_prefill`.